Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations.
The basic CMOS SRAM cell generally includes two n-type (nMOS) pull-down or drive transistors and two p-type (pMOS) load transistors in a cross-coupled inverter configuration, with two additional nMOS select or pass-gate transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation. As transistor feature sizes are continually reduced, however, achieving good, consistent cell patterning that maintains this transistor matching to avoid increased power dissipation is becoming more difficult in SRAM, despite the use of optical pattern correction (OPC) in the photolithographic process.
In operation of SRAM memory arrays, power is generally dissipated in the entire array and peripheral drive/access circuitry even as the array stands idle. This is because in the highest density arrays, power supply lines are shared row to row in common to keep real estate to a minimum. Power dissipation may be reduced while retaining data, by lowering the voltage (e.g., Vss, Vdd) to the array, such as in a data retention mode or sleep mode. In normal operations of the cells, however, a higher voltage is usually again applied to the array, and the cells are accessed via a wordline one row at a time.
Accordingly, for minimum static power dissipation in an SRAM device, it would be desirable to apply full voltage to only the row(s) being accessed, with all other rows of the array in the lower voltage data retention mode. However, the switching between the rows of such an array configuration would add latency and dynamic power. In a prior art, for example, the control of the supply voltage is provided along with the wordline access of a row, keeping the other rows of the array at the lower dissipation voltage. Another problem with this solution is that a significant amount of additional power distribution switching circuitry and wafer real estate must be provided to isolate the power lines between each row of the entire array.
An attractive compromise may be to segment the memory array into relatively small groups of rows wherein the voltage to a group is raised for access and lowered for retention. However, segmenting an array into these relatively small groups of rows may result in inconsistent patterning of the edge rows relative to rows central to the array, and may require significantly more peripheral decoder circuitry and the associated additional area penalty.
Accordingly, there is a need for an area efficient means of isolating power between relatively small groups of rows of an SRAM array while maintaining good pattern uniformity of the cells row to row, equivalent device performance, and minimal power dissipation in the fabrication of SRAM memory devices.